1. Field of the Invention
A PWM (Pulse Width Modulation) controller and a pulse waveform control method of the present invention relate particularly to a PWM controller for controlling a pulse width of a PWM signal and a pulse waveform control method for the same.
2. Description of Related Art
In these years, a strict limitation on power consumption is required for a-semiconductor device installed in a portable apparatus such as a mobile phone, in order to extend usable time of the apparatus. Such a semiconductor device receives power supply through a power supply control circuit to obtain a stable power supply, in some cases. Here, to achieve reduction in power consumption of the semiconductor device, the power supply control circuit needs to be precisely controlled so as to suppress its rapid activation and outputted voltage fluctuation. The power supply control circuit controls the power supply to the semiconductor device by sending PWM (Pulse Width Modulation) pulses to a PID (Power Intelligence Device) that is a switching element. When such a power supply control circuit precisely suppresses the outputted voltage fluctuation, the power supply control circuit needs to control the PWM pulses with a high-resolution step. However, to increase the resolution of the PWM pulses, a clock frequency to be used must be increased, thereby causing a problem of increasing the power consumption of the semiconductor device.
In this respect, Patent Document 1 has disclosed an example of the PWM controller for modulating PWM pulses. FIG. 7 shows a block diagram of the PWM controller 100 disclosed in Patent Document 1. The PWM controller 100 is a digital pulse width modulator which generates a pulse width modulation signal by modulating clock signals depending on a digital signal value. The PWM controller 100 includes a synchronization detector 101, a first counter 102, a second counter 103, a leading edge control signal generator 104, a trailing edge control signal generator 105 and a pulse width modulation signal generator 106. In addition, as the clock signals, two clock signals (a clock signal A and a clock signal B) having a frequency ratio of (N+1):N are supplied to the PWM controller 100.
The synchronization detector 101 detects timing when the clock signal A and the clock signal B synchronize with each other, and thus outputs a synchronization signal to the first counter 102 and the second counter 103. An enable signal is inputted into the synchronization detector 101. While the enable signal is asserted (effective), the synchronization detector 101 operates. The first counter 102 is initialized depending on the synchronization signal, then counts the clock signal A, and thus generates a first count signal. The second counter 103 is initialized depending on the synchronization signal, then counts the clock signal B, and thus generates a second count signal. By use of the clock signal A, the leading edge control signal generator 104 generates a leading edge control signal for identifying the pulse leading edge position of the pulse width modulation signal in accordance with the first count signal and a digital signal. By use of the clock signal B, the trailing edge control signal generator 10 generates a trailing edge control signal for identifying the trailing edge position of the pulse width modulation signal in accordance with the second count signal and the digital signal. The pulse width modulation signal generator 106 synthesizes the leading edge control signal generated by the leading edge control signal generator 104 and the trailing edge control signal generated by the trailing edge control signal generator 105, and thus generates the pulse width modulation signal.
In this respect, the clock signal A has a frequency which is {(N+1)×M} times as high as the frequency of a sampling clock of the digital signal. In addition, the clock signal B has a frequency which is {N×M} times as high as the frequency of the sampling clock of the digital signal. Note that N is the power of 2, or the power of 10. Furthermore, the digital signal represents a 16-bit digital data, for example.
In the PWM controller 100, first of all, the synchronization detector 101 detects that the rising edge position of the clock signal A and the rising edge position of the clock signal B switch positions back and forth. Subsequently, depending on this switch of positions between the edges, the synchronization detector 101 outputs the synchronization signal to the first counter 102 and the second counter 103, and thus initializes the first counter 102 and the second counter 103.
Thereafter, the first counter 102 is initialized on the basis of the synchronization signal, and starts to count the clock signal A after the initialization is completed, thereby outputting the counted number of the clock signal A as the first count value. The first count signal has a value which recurs between 0 (zero) and {(N+1)×M−1}. On the other hand, the second counter 103 is initialized on the basis of the synchronization signal, and starts to count the clock signal B after the initialization is completed, thereby outputting the counted number of the clock signal B as the second count signal. The second count signal has a value which recurs between 0 (zero) and {N×M−1}.
In this respect, the frequency ratio between the clock signal A and the clock signal B is (N+1):N. Consequently, the phase difference between the clock signal A and the clock signal B recurs with (N+1) cycles. N-step phase difference sequentially appears in units of (one cycle of the clock signal A)/N. For example, at a starting point, the phase difference between the clock signal A and the clock signal B is 0/N cycle; around the middle, the phase difference between the clock signal A and the clock signal B is (N/2)/N cycle; and at an end point, the phase difference between the clock signal A and the clock signal B is (N−1)/N cycle. Note that the first counter 102 and the second counter 103 are synchronized with each other. For this reason, if a value of the second counter 103 is identified, then it is possible to identify the phase difference between the rising edge of the clock signal B which corresponds to the value and the rising edge of the clock signal A which immediately precedes the thus-identified rising edge of the clock signal B.
Afterward, the leading edge control signal generator 104 identifies a pulse leading edge position on the basis of the digital signal. Thus, the leading edge control signal generator 104 asserts the leading edge control signal depending on the rising edge of the clock signal A which causes the position to correspond to the value of the first count signal. Subsequently, the leading edge control signal generator 104 negates the leading edge control signal at the end point of the first count signal. The trailing edge control signal generator 105 identifies a pulse trailing edge position on the basis of the digital signal. Thus, the trailing edge control signal generator 105 negates the trailing edge control signal depending on the rising edge of the clock signal B which causes the position to correspond to the value of the second count signal. Subsequently, the trailing edge control signal generator 105 asserts the trailing edge control signal at the starting point of the second count signal.
In this point, descriptions will be provided for how the PWM controller operates in a case where: N is set at 128, while M is set at 5; N and M are applied to the 16-bit digital signal. First of all, in order to calculate the pulse trailing edge position of the pulse width modulation signal, a value (in this case, {N×(M−1)−1}=128×4−1) of the second count signal at a certain synchronization time between the clock signal A and the clock signal B is summed with the data of the lower 7 digit numbers of the digital signal. Subsequently, the trailing edge control signal is negated depending on the rising edge of the clock signal B which causes this sum value to correspond to the value of the second count signal. The trailing edge control signal is asserted at the starting point of the second count signal (at a point when the counted value is 0 (zero)).
Additionally, in order to calculate the pulse leading edge position, a value (in this case, {(N+1)×(M−1)−1}=129×4−1) of the first count signal at the same synchronization time is summed with the data of the lower 7 digit numbers of the digital signal. Subsequently, data of the upper remaining 9 digit numbers of the digital signal is subtracted from the sum value. The leading edge control signal is asserted depending on the rising edge of the clock signal A which causes this subtraction value to correspond to the value of the first count signal. The leading edge control signal is negated at end point of the first count signal (at a time when the counted value is 129×5−1).
As described above, when frequency ratio between the clock signal A and the clock signal B is (N+1):N, the phase difference between the clock signal A and the clock signal B recurs with (N+1) cycles. N-step phase difference sequentially appears in units of (one cycle of the clock signal A)/N. By use of this phase difference, the PWM controller 100 is capable of generating the pulse width modulation signal whose unit is (one cycle of the clock signal A)/N. In other words, the PWM controller 100 has a resolution which is N times as high as the resolution of each period of the clock signal received by the PWM controller 100. Consequently, the PWM controller 100 is capable of controlling the pulse width with the resolution which is N times higher than by use of a clock with the same frequency.
[Patent Document 1] Japanese Patent No. 3967370